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E2F0003-27-X1
Semiconductor MSM7650
Semiconductor NTSC/PAL Digital Encoder
This version: Jan. 1998 MSM7650 Previous version: Oct. 1997
GENERAL DESCRIPTION
The MSM7650 is a digital NTSC/PAL encoder. By inputting digital image data conforming to CCIR Rep624-4, it outputs analog composite video signals and analog S video signals. For the scanning system, interlaced or noninterlaced mode can be selected. Since the MSM7650 is provided with pins dedicated to overlay function, text and graphics can be superimposed on a video signal. In addition, this encoder has an internal 9-bit DAC. So, when compared with using a conventional analog encoder, the number of components, the board space, and points of adjustment can greatly be reduced, thereby realizing a low cost and high-accuracy system. The host interface provided conforms to Philips's I2 C specifications, which reduces interconnections between this encoder and mounting components. The internal synchronization signal generator (SSG) allows the MSM7650 to operate in master or slave mode. FEATURES * Video signal system: NTSC/PAL * Scanning system: interlaced/noninterlaced * Input digital level: conforms to ITU-601 (CCIR601) * Input-output timing: conforms to CCIR Rep 624-4 * Input signal (sampling ratio) Y:Cb:Cr (4:2:2/4:1:1) * Supported sampling rates * NTSC 4Fsc (14.32 MHz) * NTSC ITU-R601 (13.5 MHz) * NTSC Square Pixel (12.27 MHz) * PAL ITU-R601 (13.5 MHz) * PAL Square Pixel (14.75 MHz) * Internal SSG circuit (internally generates sync signals) * Operation by external synchronization possible * Internal 3ch 9-bit DAC (samples by double frequency) * 3-bit title graphics can be displayed * I2C-bus host interface function * Package 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM7650GS-BK)
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Semiconductor
MSM7650
APPLICATIONS
* Video game equipment * Electronic still camera * Video printer * Video camera * Scanner * Image file system * CD-ROM * Video graphics board * Videophone * Video conference system * Multimedia equipment * Digital VTR
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BLOCK DIAGRAM
Semiconductor
RESET_L YD[7:0] CD[7:0] Y Limitter C Limitter & UV Selector OLR OLG OLB OLC VSYNC_L HSYNC_L BLANK_L CLKX1 V Level Converter YUV Color generator Y Level Converter U Level Converter Black & Blank Pedestal Interpolator + LPF Interpolator + LPF Color Burst Generator Subcarrier Generator IPF IPF DAC DAC DAC YA CVBSO CA
Overlay Control
CT [8:0]
CLKX2O Sync Generator & Timing Controller
I2C Control Logic
Test Control Logic X
CLKX2
MS
INTERLACE
MODE[2:0]
SCL
SDA
TOUT[2:1]
TEST[4:1]
MSM7650
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Semiconductor
MSM7650
PIN CONFIGURATION (TOP VIEW)
80 CD7 79 CD6 78 CD5 77 CD4 76 CD3 75 CD2 74 CD1 73 CD0 72 YD7 71 YD6 70 YD5 69 YD4 68 YD3 67 YD2 66 YD1 65 YD0
64 VDD5 63 VDD3 62 GND 61 OLR 60 OLG 59 OLB 58 OLC 57 MODE[0] 56 MODE[1] 55 MODE[2] 54 INTERLACE 53 MS 52 RESET_L 51 SCL 50 SDA 49 ADRS 48 TOUT2 47 TOUT1 46 TEST4 45 TEST3 44 TEST2 43 TEST1 42 GND 41 VDD3
VDD5 1 VDD3 2 GND 3 VSYNC_L 4 HSYNC_L 5 BLANK_L 6 CLKX1 7 CLKX2 8
CLKX2O 9 X 10 X_L 11 VDD3 12 GND 13 CT8 14 CT7 15 CT6 16 CT5 17 CT4 18 CT3 19 CT2 20 CT1 21 CT0 22 VDD5 23 GND 24
VDD3 25 NC 26
VREF 27 FS 28
COMP 29 AGND 30
YA 31 AGND 32
AVDD 33 AVDD 34 CVBSO 35
AGND 36 CA 37
AVDD 38 GND 39
NC : No-connection pin 80-Pin Plastic QFP
NC 40

MSM7650
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Semiconductor
MSM7650
PIN DESCRIPTIONS (1/2)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 to 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 I I O O I/O I I I O I I/O I/O I I I O I O I/O Symbol VDD5 VDD3 GND VSYNC_L HSYNC_L BLANK_L CLKX1 CLKX2 CLKX2O X X_L VDD3 GND CT8 to CT0 VDD5 GND VDD3 NC VREF FS COMP AGND YA AGND AVDD AVDD CVBSO AGND CA AVDD GND NC VDD3 GND TEST1 TEST2 TEST3 5.0V power supply 3.3V power supply Digital GND Vertical sync signal Polarity is negative. Output pin in master mode; input pin in slave mode. Horizontal sync signal Polarity is negative. Output pin in master mode; input pin in slave mode. Composite blank signal. Polarity is negative. Pixel clock input pin Double pixel clock input pin Double pixel clock output pin Test pin. Normally, fixed to "0". Test pin 3.3V power supply Digital GND Input pin for testing. Normally, fixed to "0" or "1". 5.0V power supply Digital GND 3.3V power supply Not connected Reference voltage for DAC DAC full scale adjustment pin DAC phase compensation pin Analog GND Analog luminance signal output pin Analog GND Analog power supply Analog power supply Analog composite video signal output pin Analog GND Analog chrominance signal output pin Analog power supply Digital GND Not connected 3.3V power supply Digital GND Input pin 1 for testing. Normally, fixed to "0". Input pin 2 for testing. Normally, fixed to "0". Input pin 3 for testing. Normally, fixed to "0". Description
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Semiconductor
MSM7650
PIN DESCRIPTIONS (2/2)
Pin 46 47 48 49 I/O I O O I Symbol TEST4 TOUT1 TOUT2 ADRS Output pin for testing Output pin for testing I2C-bus subaddress setting pin. One of two addresses switchable can be selected as subaddress. 1: 1000110/0: 1000100 50 51 52 53 54 I/O I I I I SDA SCL RESET_L MS INTERLACE I2C-bus data pin I2C-bus clock pin System reset pin. "1" at an open state by an internal pull-up resistor Operation mode select signal pin for synchronization circuit. 1: master/0: slave. "1" at an open state by an internal pull-up resistor Interlace/noninterlace select signal pin. 1: interlaced/0: noninterlaced. "1" at an open state by an internal pull-up resistor 55 to 57 I MODE[2] to MODE[0] Video mode select pins These pins are valid when MR[7] is "1". 000: NTSC CCIR 100: PAL CCIR 58 59 60 61 62 63 64 65 to 72 73 to 80 I I I I I I OLC OLB OLG OLR GND VDD3 VDD5 YD0 to YD7 CD0 to CD7 001: NTSC Square Pixel 101: PAL Square Pixel 010: NTSC 4Fsc Description Input pin 4 for testing. Normally, fixed to "0".
"000" at an open state by an internal pull-down resistor Transparent control signal Overlay signal is displayed when this pin is "H". Overlay text color (Blue component) Overlay text color (Green component) Overlay text color (Red component) Digital GND 3.3V power supply 5.0V power supply Digital image luminance signal data input pin Level is based on ITU-601. YD7 is MSB. Digital image chrominance signal data input pin Level is based on ITU-601. CD7 is MSB.
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Semiconductor
MSM7650
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Analog Output Current Power Consumption Storage Temperature Symbol VDD5 VDD3 AVDD VI IO PW TSTG Condition Ta=25C Ta=25C Ta=25C Ta=25C -- -- -- Rating -0.3 to +7 -0.3 to +4.5 -0.3 to +4.5 -0.3 to VDD5 +0.3 40 800 -55 to +150 V mA mW C V Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Symbol VDD5 VDD3 AVDD Power Supply Voltage GND AGND VIH1 High Level Input Voltage VIH2 VIH3 Low Level Input Voltage Operating Temperature Range External Reference Voltage (*1) DA Current Setting Resistance (*2) DA Output Load Resistance VIL Ta Vrefex Riadj RL Condition Ta=25C Ta=25C Ta=25C Ta=25C Ta=25C SDA, CLKX1, Except CLKX2, Ta=25C SDA, Ta=25C CLKX1,CLKX2, Ta=25C -- -- -- -- -- 0.8VDD5 2.4 0.0 0.0 -- -- -- -- -- -- -- 1.25 330 75 VDD5 VDD5 0.5 70 -- -- -- V V V C V W W 2.2 -- VDD5 V Min. 4.5 3.0 3.0 -- -- Typ. 5.0 3.3 3.3 0.0 0.0 Max. 5.5 3.6 3.6 -- -- V V Unit
(*1)
When external reference voltage is not supplied, internal reference voltage is as follows.
Vrefin -- 1.15 -- 1.45 V
Internal Reference Voltage
(*2)
A volume control resistor of approx. 500W is recommendable for adjusting the output current.
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Semiconductor
MSM7650
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta=0 to +70C, VDD3=3.3V0.3V, VDD5=5V10%) Parameter High Level Output Voltage Low Level Output Voltage Input Leak Current Output Leak Current Power Supply Current (operating) Power Supply Current (standby) I2 C-bus SDA Output Voltage I2C-bus SDA Output Current Internal Reference Voltage DA Output Load Resistance Integral Linearity Differential Linearity Symbol VOH VOL II IO IDDO IDDS SDAVL SDAIO Vrefin RL SINL SDNL Condition IOH=-4mA (*1) IOH=-8mA (*2) IOL=4mA (*1) IOL=8mA (*2) VI=GND to VDD5 VI=GND to VDD5 (*3) CLKX1=13.5MHz CLKX2=27.0MHz RESET_L="L" CLKX1=CLKX2=0Hz Low level, IOL=3mA During Acknowledge -- -- Min. 0.8VDD5 0 -10 -10 -- -- 0 3 1.15 Typ. -- -- -- -- 120 65 -- -- -- 75 2 1 Max. VDD5 0.6 10 10 140 80 0.4 -- 1.45 Unit V V mA mA mA mA V mA V W LSB LSB
(*1) (*2) (*3)
HSYNC_L, VSYNC_L, SDA, TO, CT[7:0] CLKX2O SDA
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Semiconductor AC Characteristics
MSM7650
(Ta=0 to +70C, VDD3=3.3V0.3V, VDD5=5V0.5V) Parameter Symbol Condition PAL Square Pixel CLKX Cycle Time TS NTSC 4Fsc NTSC Square Pixel ITU-RS601 Input Data Setup Time Input Data Hold Time Output Delay Time CLKX2O Delay Time Clock Cycle Time Clock Duty Cycle Low Level Cycle ts1 th1 td1 td2 tC_SCL tD_SCL tL_SCL Rpull_up=4.7kW -- -- -- -- Rpull_up=4.7kW Min. -- -- -- -- 7.03 9.48 18.35 7.69 200 -- 100 50 -- Typ. Max. 67.8 69.8 81.5 74.1 -- -- -- -- -- -- -- -- -- -- 24.12 9.53 Unit ns ns ns ns ns ns ns ns ns % ns
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Semiconductor
CLKX1
Input timing
RESET_L, HSYNC_L, VSYNC_L, YD[7:0], CD[7:0], MS, MODE[2:0], INTERLACE, OLR, OLG, OLB, OLC HSYNC_L, VSYNC_L
Output timing
CLKX2
CLKX2O
MSM7650
ts1 valid th1 invalid td1 valid td2 tC_SCL tL_SCL
SCL
SDA
The phase relations between CLKX1 and CLKX2 are shown below. 1. When the CLKX1 pulse rises later than the CLKX2 pulse.
CLKX2
Tccd1
CLKX1
2.
When the CLKX1 pulse rises earlier than the CLKX2 pulse.
CLKX2
Tccd2
CLKX1
Tccd1: 20.14 [ns] Tccd2: 3.27 [ns]
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Semiconductor
MSM7650
BLOCK FUNCTIONAL DESCRIPTION
Y Limitter This block limits the contents outside the specified range as follows for input luminance signal YD specified by the ITU-601 standard. * Signals are limited to YD = 235 when YD_IN > 235 * Signals are limited to YD = 16 when YD_IN < 16 * In other cases, signals are fed as is to next processing C Limitter This block limits the contents outside the specified range as follows for input chrominance signals specified by the ITU-601 standard. The input chrominance signal is output as a 2's complement format. The processing procedure follows. 1) Format processing for input chrominance signals * If MR [6] = 0, CD is in offset binary format. CD is converted to 2's complement format and is fed to next processing. * If MR [6] = 1, CD is in 2's complement format. CD is fed as is to next processing. 2) * * * Clipping processing Signals are limited to CD = 112 when CD>112 Signals are limited to CD = -112 when CD < -112 In other cases, signals are fed to next processing
In addition, this block separates U and V components from the input chrominance signal CD into which data of U and V components has been inserted using time sharing, and then passes signals to the next process. * Y Level Converter Converts ITU-601 standard luminance signal level to DAC digital input level. * U Level Converter Converts ITU-601 standard chrominance signal level to DAC digital input level. * V Level Converter Converts ITU-601 standard chrominance signal level to DAC digital input level. * YUV Color Generator This block generates luminance and chrominance signals from over lay color signals OLR, OLG and OLB. Control signals (CR [2:0] ) control the output content (overlay or color bar) and output level (100%, 75%, 50%, 25%). * Overlay Control This block selects input image data or YUV Color Generator output signals. It is determined by the level of the control signal (OLC, CR [2]), as shown below: CR [2] = 1, OLC = ?: Selects color bar signal (YUV Color Generator output signal). CR [2] = 0, OLC = 1: Selects overlay signal (YUV Color Generator output signal). CR [2] = 0, OLC = 0: Selects input image data. 11/34
Semiconductor * Black & Blank Pedestal This block adds sync signals at the luminance side to luminance signals.
MSM7650
* Interpolator +LPF This block executes data interpolation and the elimination of high frequency components by LPF for input chrominance signals. Both 4:2:2 and 4:1:1 signals are processed. * I2C Control Logic This is the serial interface block based on I2C standard of Phillips Corporation. Internal registers MR and CR can be set from the master side. When writing to the internal registers other than MR [5] (black level control) and CR [1:0] (overlay level), written contents are immediately set to them. It is during the vertical blanking period that written contents are set to MR [5] and CR [1:0]. * Sync Generator & Timing Controller This block generates sync signals and control signals. This block is operated in slave mode, which performs external synchronization, and in master mode, which internally generates sync signals. * Color Burst Generator Outputs U and V components of amplitude of burst signals. * Subcarrier Generator Executes color subcarrier generation. * Interpolation Filter (IPF) This block performs upsampling at CLK X 2 (double speed CLKX1) for luminance signals and chrominance signals modulated with CLKX1. Interpolation processing is executed in this process.
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Semiconductor
MSM7650
INPUT DATA FORMAT Input Digital Level
The content conforms to CCIR601 (ITU-601). For chrominance input Cb and Cr, 2's complement and offset binary formats are available by setting of internal registers. Input values outside the specified range are limited by internal clipping processing. The valid input levels of luminance signal and chrominance signal are shown below.
Digital Level 100% White level 235 240(112) Digital Level
128(0)
Black Level 16 Y data 16(-112) C data Note) Values are in offset binary format. (Values in parenthesis are in 2's complement format.)
Input luminance signal level
Input chrominance signal level
Basic Pixel Sampling Ratio
4:2:2 and 4:1:1 sampling are supported. An internal register can control the sampling ratio.
CLKX1 YD CD Y1 U1 Y2 V1 Y3 U3 Y4 V3 Y5 U5 Y6 V5 CLKX1 YD CD Y1 U1 Y2 V1 Y3 Y4 Y5 U5 Y6 V5
4:2:2 sampling
4:1:1 sampling
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Semiconductor
MSM7650
OUTPUT FORMAT Output Level
When the output level of the operation mode is NTSC, the content of the output level differs depending on setup level setting by internal registers. When the setup level is set, data is output with Black-White as 92.5 IRE. When the setup level is not set, data is output with Black-White as 100 IRE. However, the setup level setting above is valid only when NTSC is selected as operation mode, and setup level does not exist when PAL is selected as the operation mode. When the contents of 100% luminance order color bar are input to the encoder, the DAC input level is as follows.
DAC data Lumi [IRE] 480 133 Composite Wave Form (NTSC) White Yellow Cyan Green Magenta Red Blue Black
389 359 307 276 227 197 169 144 135 114 59 4
100 89 70 59 41 30 20 11 7.5 0 -20 -40
NTSC composite signal (setup: 7.5 IRE)
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Semiconductor
MSM7650
DAC data Lumi [IRE] 389 359 307 276 227 197 144 114 100 89 70 59 41 30 11 0
Y Wave Form (NTSC) White Yellow Cyan Green Magenta Red Blue Black
4
-40
NTSC Y signal output (setup: 0)
DAC data Lumi [IRE] 429 418 377 311 256 201 135 94 83 63 59 44 20 0 -20 -44 -59 -63
C Wave Form (NTSC) Yellow Cyan
Green Magenta
Red Blue
Color Burst
NTSC C signal output (setup: 0)
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Semiconductor
MSM7650
DAC data Lumi [IRE] 488 133
Composite Wave Form (PAL) White
Yellow Cyan
Green Magenta
Red Blue
Black
397 367 315 285 235 205 181 153 122 63 4
100 89 70 59 41 30 21.5 11 0 -21.5 -43
PAL composite signal
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Semiconductor
MSM7650
DAC data Lumi [IRE] 397 367 315 285 235 205 153 122 100 89 70 59 41 30 11 0
Y Wave Form (PAL) White Yellow Cyan Green Magenta Red Blue Black
4
-43
PAL Y signal output
DAC data Lumi [IRE] 429 418 377 315 256 197 135 94 83 63 59 44 21.5 0 -21.5 -44 -59 -63
C Wave Form (PAL) Yellow Cyan
Green Magenta
Red Blue
Color Burst
PAL C signal output
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Semiconductor
MSM7650
CLOCK TIMING Input Data Timing
Input data and sync signals are fed into the encoder at the rising edge of the clock. Input data is handled as valid pixel data when tSTART passes after the falling edge of HSYNC_L. Chrominance signal of input data at this time is regarded as Cb.
ACTIVE VIDEO LINE tACT
tSTART CLKX1 HSYNC_L YD, CD OLC, OLR OLG, OLB BLANK_L ts1 don't care
th1 don't care VALID DATA
Video data input timing Input data is recognized as valid pixel data when input signal BLANK_L is high in the tACT period. When BLANK_L is high during the blanking period, however, input data is not output as valid pixel data since processing to maintain blanking period is internally in-progress. The values of tSTART differ slightly in master mode and slave mode. The values of tSTART are as follows.
In master mode Operation mode CCIR 601 NTSC Square Pixel NTSC 4Fsc NTSC CCIR PAL Square Pixel PAL tSTA-tS1=tSTART tSTA(Ts) 126 141 115 134 154 In slave mode Operation mode CCIR 601 NTSC Square Pixel NTSC 4Fsc NTSC CCIR PAL Square Pixel PAL tSTA(Ts) 129 144 118 137 157
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Semiconductor
MSM7650
Internal Synchronization Output Timing
Input and output timing of HSYNC_L and VSYNC_L in master mode is as follows.
CLKX1 td1 HSYNC_L VSYNC_L td1
Output timing of internal synchronization CLK1, HSYNC_L and VSYNC_L
VSYNC_L
YA
523 524 525 1 2 3 4 5 6 7 17 18
Output timing of internal synchronization VSYNC_L
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Semiconductor
MSM7650
Output Timing
Output timing conforms to CCIR Rep 624-4. When the operation method is NTSC/PAL and the scanning method is interlace/noninterlace, the output wave form content of composite signals are as follows.
Field 1 NEGATIVE HALF CYCLE Burst relative 180 to B-Y axis POSITIVE HALF CYCLE Burst relative 180 to B-Y axis
Reference sub-carrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E Field 2 Reference sub-carrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E Field 3 Reference sub-carrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E Field 4 Reference sub-carrier phase
259
260
261 A
262 263
1
2 B D
3
4
5 C
6
7
8
17
18
19
E
Output timing (interlaced NTSC)
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Semiconductor
MSM7650
Symbol A B C D E
Name First equalizing pulse period (3H) Vertical synchronization period (3H) Second equalizing pulse period (3H) Burst pause period Vertical blanking period (20H)
Period Odd field (Even field) 259.5 to 262.5H 1 to 3H 4 to 6H 1 to 6,259.5 to 262.5H 1 to 17,259.5 to 262.5H
Output timing (interlaced NTSC)
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Semiconductor
MSM7650
Continuous Odd Field
NEGATIVE HALF CYCLE Burst relative 180 to B-Y axis Reference sub-carrier phase
POSITIVE HALF CYCLE Burst relative 180 to B-Y axis
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Reference sub-carrier phase
260
261 A
262
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Continuous Even Field
Reference sub-carrier phase
260
261
262 A
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Reference sub-carrier phase
260
261
262 A
1
2 B D
3
4
5 C E
6
7
8
17
18
19
Output timing (noninterlaced NTSC)
Period Continuous odd field 261 to 262H 1 to 3H 4 to 6H 261 to 6H 261 to 17H Continuous even field 261.5 to 262H 1 to 3H 4 to 6H 261.5 to 6H 261.5 to 17.5H
Symbol A B C D E
Name First equalizing pulse period (2H) Vertical synchronization period (3H) Second equalizing pulse period (2H) Burst pause period Vertical blanking period (19H)
Output timing (noninterlaced NTSC)
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Semiconductor
MSM7650
Field 1,5
burst phase +135 +V
burst phase -135 -V
309
310
311
312 313 A
1 B
2
3
4 C
5
6
7
8
23
24
25
D E Field 2,6
309
310
311
312 313 A
1 B D
2
3
4 C E
5
6
7
8
23
24
25
Field 3,7
309
310
311
312 313 A
1 B D
2
3
4 C E
5
6
7
8
23
24
25
Field 4,8
309
310
311
312 313 A
1 B
2
3
4 C
5
6
7
8
23
24
25
D E
Output timing (Interlaced PAL)
Symbol A B C D E Name Filed 1,5 First equalizing pulse period (2.5H) Vertical synchronization period (2.5H) Second equalizing pulse period (2.5H) Burst pause period Vertical blanking period (25H) 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 6,310 to 312.5H 1 to 22.5,311 to 312.5H Filed 2,6 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 5.5,308.5 to 312.5H 1 to 22.5,311 to 312.5H Period Filed 3,7 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 5,311 to 312.5H 1 to 22.5,311 to 312.5H Filed 4,8 311 to 312.5H 1 to 2.5H 2.5 to 5H 1 to 6.5,309.5 to 312.5H 1 to 22.5,311 to 312.5H
Output timing (Interlaced PAL)
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Semiconductor
MSM7650
Continuous Odd Field
burst phase +135 +V
burst phase -135 -V
309
310
311 A
312
1 B
2
3
4 C
5
6
7
8
23
24
25
D E
309
310
311 A
312
1 B
2
3
4 C
5
6
7
8
23
24
25
D E Continuous Even Field
309
310
311 A
312
1 B
2
3
4 C
5
6
7
8
23
24
25
D E
309
310
311 A
312
1 B
2
3
4 C
5
6
7
8
23
24
25
D E
Output timing (Noninterlaced PAL)
Period Continuous odd field 311 to 312H 1 to 2.5H 2.5 to 5H 311 to 6H 311 to 22H Continuous even field 311.5 to 312H 1 to 2.5H 2.5 to 5H 311.5 to 6H 311.5 to 22.5H
Symbol A B C D E
Name First equalizing pulse period (2H) Vertical synchronization period (2.5H) Second equalizing pulse period (2.5H) Burst pause period Vertical blanking period (24H)
Output timing (Noninterlaced PAL)
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Semiconductor Equalizing pulse vertical synchronization period
q w e r q 1/2H w 1/2H e
MSM7650
Setting content of equalizing pulse vertical synchronization period (Ts is sampling clock cycle in each mode) q NTSC CCIR601 PAL CCIR601 w e 1/2H 31Ts 398Ts 64Ts 429Ts 32Ts 369Ts 63Ts 432Ts 28Ts 332Ts 58Ts 390Ts 33Ts 387Ts 68Ts 455Ts 35Ts 403Ts 69Ts 472Ts
NTSC Square Pixel qEqualizing pulse width qblanking level NTSC 4Fsc wVertical sync pulse width w(synchronizing+{blanking level) (2/3) e(synchronizing+{blanking level) (1/3) PAL Square Pixel eSerration rSynchronzing level
Equalizing pulse vertical synchronization period
1H
Equalizing pulse vertical synchronization period
r e w q
t
q e r
w
t qHorizontal sync pulse width wBurst signal output period eBurst signal start rHorizontal blanking period (excluding front porch) tFront porch start qSynchronzing level w(synchronizing+{blanking level) (1/3) e(synchronizing+{blanking level) (2/3) rblanking level tpeak to peak value of burst
Horizontal blanking period
Setting content of horizontal blanking period (Ts is sampling clock cycle in each mode) q NTSC CCIR601 PAL CCIR601 NTSC Square Pixel NTSC 4Fsc PAL Square Pixel 63Ts 63Ts 58Ts 67Ts 69Ts w 31Ts 31Ts 31Ts 36Ts 34Ts e r t Total dots/1H 858 864 780 910 944 71Ts 127Ts 838Ts 75Ts 142Ts 844Ts 65Ts 116Ts 762Ts 75Ts 135Ts 889Ts 82Ts 155Ts 922Ts
Setting content of horizontal blanking period 25/34
Semiconductor
MSM7650
Internally Generated Color Bar Output Timing
This function outputs a 100% and 75% luminance order color bar by setting internal registers. Output timing of each color of the color bar is as follows.
White Yellow Cyan Green Red Blue Black
Magenta
q w e r t y u
Each color of color bar output timing
Operation mode NTSC CCIR601 NTSC Square Pixel NTSC 4Fsc PAL CCIR601 PAL Square Pixel
hblank 127Ts 116Ts 135Ts 142Ts 155Ts
q 216Ts 197Ts 230Ts 230Ts 251Ts
w 305Ts 278Ts 325Ts 318Ts 347Ts
e 394Ts 359Ts 419Ts 406Ts 443Ts
r 483Ts 440Ts 513Ts 494Ts 539Ts
t 572Ts 521Ts 607Ts 582Ts 635Ts
y 661Ts 602Ts 701Ts 670Ts 731Ts
u 750Ts 682Ts 795Ts 757Ts 827Ts
1H 858Ts 780Ts 910Ts 864Ts 944Ts
(Ts is sampling clock cycle)
Each color of color bar output timing
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Semiconductor
MSM7650
I2C-bus Interface Input/Output Timing
Basic input/output timing of I2C-bus interface is shown below.
SDA SCL MSB
S Start Condition
1
2
7
8
9 ACK tC.SCL
1 tL.SCL
2 3-8
9 ACK
P Stop Condition
Data Line Stable: Data Valid Change of Data Allowed
I2C-bus basic input/output timing
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Semiconductor
MSM7650
I2C BUS FORMAT
Basic input format of I2C-bus interface is shown below.
1 cycle S Slave Address A S Symbol S Slave Address A Subaddress Data n P Start condition Slave address 1000100 or 1000000, 8th bit is write signal. Acknowledge. Generated by slave Subaddress byte Data byte and acknowledge continues until data byte stop condition is met. Stop condition Subaddress0 Slave Address A A Data 0 Subaddress1 Description A P A Data 1 A P .....
It is required to input the above-mentioned format from the start condition to the stop condition each time of writing a subaddress. For example, when writing the subaddresses 0 to 2, the format should be input three times. In case data of more than one byte are transferred,
S Slave Address A Subaddress0 A Data 0 A P Data n A P
The 4th byte data and following data each are written over the same subaddress. If one of the following matters occurs, the encoder will not return "A" (Acknowledge). * The slave address does not match. * A non-existent subaddress is specified. * The read/write attribute of a register does not match "X" (read/write control bit). The input timing is shown below.
SDA SCL
1
2
8
ACK
1
2
8
ACK
1
2
8
ACK
S Start Condition
Slave Address
Sub Address
Data
P Stop Condition
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Semiconductor
MSM7650
CONTENTS OF INTERNAL REGISTER SETTING
All registers can be written by accessing 8 bits. "0" is read from an undefined bit. The contents of internal registers are shown below. (A value with "*" is the default.)
Mode Register (MR) (Default value after system reset: 10H) MR[7] Override Selects setting of external terminal or internal register *0: setting of external terminal is valid 1: setting of internal registers is valid
MR[6]
Chroma format
Chrominance signal input format *0: Offset binary 1: 2's Complement
MR[5]
Black level control
Black level setting (setup) Note) Valid only for NTSC. *0: Black level 7.5 IRE 1: Black level 0 IRE
MR[4]
Synchronization mode
Selects master/slave operation of sync signal generator. 0: slave mode *1: master mode
MR[3]
Pixel sampling ratio
Sampling ratio *0: 4:2:2 1: 4:1:1
MR[2:0]
Video mode select
Selects operation mode *000: CCIR 601 NTSC 13.5 MHz 001: NTSC Square Pixel 12.27 MHz 010: NTSC 4Fsc 14.32 MHz 100: CCIR 601 PAL 13.5 MHz 101: PAL Square Pixel 14.75 MHz
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Semiconductor Command Register (CR) (Default value after system reset: 1BH) CR[7:5] Undefined Undefined
MSM7650
CR[4]
Genlock
Selects SCH phase management status 0: Genlock Off (subcarrier is self generated) *1: Genlock On (management of SCH phase is executed)
CR[3]
Non-Interlace
Scanning method in master mode 0: Non-Interlace *1: Interlace
CR[2]
Color bar
Output control of luminance order color bar for adjustment *0: input image data or overlay data 1: luminance order color bar
CR[1:0]
Overlay level
Luminance signal output level control of overlay signals and luminance order color bar for adjustment 00: 25% 01: 50% 10: 75% *11: 100%
Register function Mode Register (MR) Command Register (CR)
Subaddress 0 1
Data byte D7 MR7 CR7 D6 MR6 CR6 D5 MR5 CR5 D4 MR4 CR4 D3 MR3 CR3 D2 MR2 CR2 D1 MR1 CR1 D0 MR0 CR0
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Semiconductor
MSM7650
FILTER CHARACTERISTICS
The characteristics of LPF used for color signal processing and interpolation filters used for upsampling processing are shown below. LPF for 411 color signals The following characteristics are when the clock frequency is 13.5 MHz.
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 Frequency [MHz] 5 6 7
411 Interpolation+LPF Frequency Characteristic
LPF for 422 color signals The following characteristics are when the clock frequency is 13.5 MHz.
0
-20
Level [dB]
-40
-60
-80
-100 0 1 2 3 4 Frequency [MHz] 5 6 7
422 Interpolation + LPF Frequency Characteristic
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Semiconductor Up Sampling Filter The following characteristics are when the clock frequency is 27 MHz.
0
MSM7650
-20
Level [dB]
-40
-60
-80
-100 0 2 4 6 8 Frequency [MHz] 10 12 14
Up Sampling Filter Frequency Characteristic
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Semiconductor
MSM7650
APPLICATION CIRCUIT EXAMPLE
5V 5V RI I2C Controller RI 5V 3.3V 3.3V
DIP SW
MODE[2:0] MS INTERLACE OLR OLG OLB OLC
VREF
External reference Typ. 1.25V voltage
VDD5
VDD3
AVDD
SDA
SCL
FS RC COMP LPF YA MSM7650 R1 LPF CVBSO R2 LPF AMP CA R2 X GND AGND CLKX2 AMP AMP CC
Overlay Controller
YD[7:0] CD[7:0]
YD[7:0] CD[7:0] CLKX1 VSYNC_L HSYNC_L BLANK_L
Recommended Analog Output Circuit
+AVCC
0.1mF YA, CA, CVBSO 150W 164pF 164pF 3.6mH 150W + - 75W 560W
1000pF +
OUTPUT
560W 0.1mF -AVCC
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Semiconductor
MSM7650
PACKAGE OUTLINES AND DIMENSIONS
25.00.2 20.00.2 ^4 $1 $0 ^5
1.0TYP.
19.00.2
14.00.2
*0
q INDEX MARK Mirror finished surface 0.8TYP.
0.170.05
0.05 to 0.35
0.25
0.8 0.12 2.5TYP.
@5 @4 0.32
+0.08 -0.07
0.16
M
SEATING PLANE
2.5MAX.
2.10.2
0 to 10
1.3TYP. 1.380.15
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